This invention relates to a semiconductor device in which a digital control power source is formed.
For example, PWM (Pulse Width Modulation) control in an analog power source is performed by comparison of triangle wave and feedback voltage (for example, Patent document 1 (JP-A 2001-251370 (Kokai)). In this case, a pulse width realized by analog PWM circuit can continuously change.
On the other hand, in a PWM circuit in a digital power source, time can be merely set discretely. When the PWM control is performed by using a clock, the clock of 1 GHz becomes required for realizing a time resolution of 1 nanosecond, and the clock of 10 GHz becomes required for realizing a time resolution of 100 picoseconds. In forming a circuit generating a clock having such a high frequency on a semiconductor substrate, a most-advanced process is required, and there is a problem that the consumption current increases for operation by the clock.
Moreover, conventionally, a plurality of power sources are connected in parallel. For example, when ten power sources having an output current of 10 ampere are operated in parallel, a power source having an output current of 100 ampere can be composed.
A current digital power IC having a parallel running function is “Master Control Architecture” composed of one master IC controlling switching of all of the phases and a plurality of driver ICs. A problem thereof is that the power system becomes failed in itself if a trouble is caused in the master IC from any cause.
Moreover, in Non-patent document 1 (“Current Sharing in Digitally Controlled Masterless Multi-phase DC-DC Converters”, Power Electronics Specialists Conference, 2005. PESC '05. IEEE 36th), a masterless architecture in which a plurality of ICs each having capability of becoming the master are connected in parallel to realize parallel running has been disclosed. However, a master clock is input from the outside, and the current information is shared among the power ICs (the phases) through a high-speed digital bath, and therefore, the number of terminals is large and the power consumption is also large.
Moreover, reference voltage used for controlling the output voltage to converge to be a target value is generalized (shared) among the power source ICs. This leads to increase of the number of the terminals in actual productization, and the reference voltage-shared terminals are affected by, wiring resistance on the substrate, parasitic capacitance, and noise, and therefore, it is necessary to care for wiring among the power ICs and the design is troublesome.
Moreover, in the case of multi-phase operation, its interleaving setting is performed by setting outside the power ICs, and if a trouble is caused in any one of the phases from any cause, the power system becomes failed in itself, and therefore, the advantage of the masterless architecture has been lost.